Finishing up RS232 receive buffer : FPGA

60 BTC tip for VHDL ASIC working design

Continued from http://www.reddit.com/Bitcoin/comments/1e5qim/reverse_engineering_of_avalon_asic_chip_work_in/
You guys convinced me that the best way to achieve the goals stated in the previous post is to design the ASIC chip from scratch, or based on a FPGA VHDL design, instead of reverse engineering it.
Here is a reference to a relevant FPGA design opensource resource :
https://github.com/fpgamineOpen-Source-FPGA-Bitcoin-Miner
And also the original FPGA which the Avalon ASIC is the evolution for, and for which there are schematics and documentation available at :
https://github.com/ngzhang/Icarus
So i'm offering a 100 BTC tip to anyone who can put out a VHDL Bitcoin miner working design conforming to the avalon specs at
https://github.com/BitSyncom/avalon-ref/
Thank you in advance for your response! This is an amazing community!
Cheers
EDIT Opensourcing the ASIC chip design is indeed something that will happen according to our roadmap and milestones reached. At any further revision of the chip the previous generation would be opensourced.
Added link to FPGA github resource mentioned in the comments.
Since i received several critics regarding the size of the tip/bounty, i have modified the amount a bit. Thank you!
submitted by whyasic to Bitcoin [link] [comments]

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